The growing use of semiconductor devices has resulted in requirements for higher speed and higher density devices. High density devices are realized by the drastic improvements achieved in photolithographic technologies which now permit of extreme microminiaturization of the geometries of patterned layers of the devices. In order to implement such shrunk design rules for semiconductor devices, a variety of planarization techniques have been proposed and put into practice to alleviate the irregularities of topography of the devices. Most responsible for such irregularities of device topography are the presence of conductor layers such as contracts and interconnections which form step portions on the surface of a semiconductor substrate.